16-09-2020, 03:22 PM
(This post was last modified: 16-09-2020, 03:25 PM by ppppenguin.)
May I run an idea past you?
The raw digital video output from the decoder chip has sync tip at nominal 0, black at approx 60 and white at approx 200, expressed as 8 bit numbers.
When I detect what appears to be the start of a sync pulse, start a counter that will run for about 30us and then stop. This is more than a line sync pulse but less than a broad pulse. While counter is running, accumulate the total of the digital values of each pixel. In an ideal broad pulse this would be zero. If not a broad pulse it would be huge. Set a threshold at which I declare it to be a broad pulse. This would allow for odd splats of dropout etc. I'd make the threshold variable for experiments.
Implementing this in a FPGA is actually very simple. The adder/accumulator would only need to be 17 or possibly 18 bits, plus comparator and ancillary bit of logic. Maybe a dozen lines of VHDL which will synthesise a negligible amount of logic, even in the modest FPGA that I'm using.
Obviously any splat ont eh signal that gets detected as a sync edge will start the count. Unless it's a broad pulse it's unlikely that the accumulated value will stay below threshold. Also once I've successfully detected a field sync, I can then lock out the sync edge detector until I expect another V sync. This will cause a delay in locking to a new signal but should minimise the risk of a finding a spurious field pulse.
Next thing is to dream up a ruggedised odd/even field detector. Unlike a monitor which has no need to know which field is odd or even, I do need to know as each field has to be stored in the correct bit of memory.
PS: Some of the point of this is not necessarily to have the crowd tear my ideas to pieces (though that is welcome) but to force myself to explain (to me!) what I'm doing. If I can't put the idea down in print or explain it to somebody else I don't really have a hope in hell of understanding what I was trying to do.
The raw digital video output from the decoder chip has sync tip at nominal 0, black at approx 60 and white at approx 200, expressed as 8 bit numbers.
When I detect what appears to be the start of a sync pulse, start a counter that will run for about 30us and then stop. This is more than a line sync pulse but less than a broad pulse. While counter is running, accumulate the total of the digital values of each pixel. In an ideal broad pulse this would be zero. If not a broad pulse it would be huge. Set a threshold at which I declare it to be a broad pulse. This would allow for odd splats of dropout etc. I'd make the threshold variable for experiments.
Implementing this in a FPGA is actually very simple. The adder/accumulator would only need to be 17 or possibly 18 bits, plus comparator and ancillary bit of logic. Maybe a dozen lines of VHDL which will synthesise a negligible amount of logic, even in the modest FPGA that I'm using.
Obviously any splat ont eh signal that gets detected as a sync edge will start the count. Unless it's a broad pulse it's unlikely that the accumulated value will stay below threshold. Also once I've successfully detected a field sync, I can then lock out the sync edge detector until I expect another V sync. This will cause a delay in locking to a new signal but should minimise the risk of a finding a spurious field pulse.
Next thing is to dream up a ruggedised odd/even field detector. Unlike a monitor which has no need to know which field is odd or even, I do need to know as each field has to be stored in the correct bit of memory.
PS: Some of the point of this is not necessarily to have the crowd tear my ideas to pieces (though that is welcome) but to force myself to explain (to me!) what I'm doing. If I can't put the idea down in print or explain it to somebody else I don't really have a hope in hell of understanding what I was trying to do.
www.borinsky.co.uk Jeffrey Borinsky www.becg.tv
