14-08-2019, 07:31 PM
Got back to this today. While the H sync from the decoder is fine, the V sync is definitely not. This accounts for the bad interpolation and horrible movement judder.
I took a closer look at the sync pulses available at various pins of the SAA7118. The V sync is a strange pattern of some pulses correctly timed and others that are part way through the field. I thinkt he whole thing is repeating on a 3 or 6 field sequence. The odd/even is even stranger. It's 60ms and 60ms down as far as I can tell.
Not unexpected I suppose. The SAA7118 has nothing that knows how to handle a 405 line signal. It's a miracle it's doing as well as it is. There are 3 lines of attack:
1: Ferret through the squillions of settings in the chip to see if anything helps. Probably a fruitless search.
2: Give up on a pure solution and add a LM1881 to do the V sync sep.
3: The SAA7118 has some settings that allow the raw data from the ADCs to be passed to the output. Assuming the syncs are digitised (and they ought to be for the rest of the chip to work) I can do the sync separation in the FPGA. Simply slicing at a particular digital level may not be ideal but it's a first attempt.
This last is most promising. The SAA7118 is doing clock generation, probably the most critical part of the whole input system. Though I'm probably going to lose the benefits of oversampling in the ADC as I don't have anything like enough resource in the FPGA to do a decent decimation filter. That needs multipliers and the XC2S200 doesn't have any. Each one would have to be synthsised and they take a lot of logic.
I took a closer look at the sync pulses available at various pins of the SAA7118. The V sync is a strange pattern of some pulses correctly timed and others that are part way through the field. I thinkt he whole thing is repeating on a 3 or 6 field sequence. The odd/even is even stranger. It's 60ms and 60ms down as far as I can tell.
Not unexpected I suppose. The SAA7118 has nothing that knows how to handle a 405 line signal. It's a miracle it's doing as well as it is. There are 3 lines of attack:
1: Ferret through the squillions of settings in the chip to see if anything helps. Probably a fruitless search.
2: Give up on a pure solution and add a LM1881 to do the V sync sep.
3: The SAA7118 has some settings that allow the raw data from the ADCs to be passed to the output. Assuming the syncs are digitised (and they ought to be for the rest of the chip to work) I can do the sync separation in the FPGA. Simply slicing at a particular digital level may not be ideal but it's a first attempt.
This last is most promising. The SAA7118 is doing clock generation, probably the most critical part of the whole input system. Though I'm probably going to lose the benefits of oversampling in the ADC as I don't have anything like enough resource in the FPGA to do a decent decimation filter. That needs multipliers and the XC2S200 doesn't have any. Each one would have to be synthsised and they take a lot of logic.
www.borinsky.co.uk Jeffrey Borinsky www.becg.tv
