405 to 625 conversion

[ppppenguin]

I suppose that's where I have an advantage. Because I have a framestore the input and output clocks can be completely separate. On Frank's linestore design (and Aurora SCRF for that matter) the output clock has to be derived from the input clock. I have a 54MHz xtal which I double to 108MHz in a XIlinx DLL. For 405 out I use a DTO to provide 27*(405/625) for all the output logic. For 405 in I use a DTO to give 24.576 *(405/625) for the SAA7118 decoder chip. I haven't even looked at the clock output of the decoder to see if the SAA7118 has passed or suppressed the 9ns jitter.