10-08-2019, 09:38 AM
Hi Refugee
The waveform does have a pattern to it. When the clock frequency feeding the video decoder is changed the pattern does not appear to change.
Hi Jeffrey
In this case the clock driving the video decoder is produced by a PLL and to give it the best chance leaves the FPGA via a designated PLL output pin. so is clean. I scoped it just to check.
A clock of 9.272876 MHz which is close to 9.27818064MHz wont work. I have to go down in frequency to 9.264706 MHz to get it to work.
The jitter in the video clock as far as I can tell cant be seen on the picture. But what may be a problem is I derive the clock for the output of the converter from the video clock and the PLL may not like the jitter.
Frank
The waveform does have a pattern to it. When the clock frequency feeding the video decoder is changed the pattern does not appear to change.
Hi Jeffrey
In this case the clock driving the video decoder is produced by a PLL and to give it the best chance leaves the FPGA via a designated PLL output pin. so is clean. I scoped it just to check.
A clock of 9.272876 MHz which is close to 9.27818064MHz wont work. I have to go down in frequency to 9.264706 MHz to get it to work.
The jitter in the video clock as far as I can tell cant be seen on the picture. But what may be a problem is I derive the clock for the output of the converter from the video clock and the PLL may not like the jitter.
Frank
