405 to 625 conversion

[ppppenguin]

I've been doing some work on 405 to 625 conversion. The attached photo shows result of first attempt. the interpolation is horrible but that should just be a matter of tweaking the interpolator coefficients. There are also problems relating to vertical sync and position which I hope won't be a huge problem. The 405 input to my converter is from an Aurora that's converting 625 line TCF down to 405.

The important point is that I did this without building a dedicated 405 line front end. I used the experimental 625 to 405 converter that I built a few years ago as the basis of my design. This in turn uses the hardware from a professional deisgn I did for a client. (The last generation of TBC/standards converters that I did for G2 Video Systems.) This uses a Philips SAA7118 as the analogue video input. It's designed for 625 and 525 only so I had doubts about how it would handle 405. If you stick 405 into it, the result is pretty much nothing. So what's the magic sauce?

I had the lightbulb moment last week. The SAA7118 uses a 24.576MHz xtal as its master clock. Everything else, including the 27MHz video clock output is derived from that. The actual xtal isn't phaselocked, you can use any source of 24.576MHz, so what happens if you feed (405/625) * 24.576MHz into the chip? I hooked up a signal generator, actually the output of my network analyser which is both precise and easily variable. After a very minor change to the logic in the FPGA, relating to video presence detection, there were pictures on the screen! Not full height and in the wrong place veritcally but that's just a question of tweaking some numbers in the interpolator. Easily done with my debug software. The result is what you see.

The 15.925MHz clock for the SAA7118 will be generated in the FPGA using a DTO from the 108MHz clock that's available. As far as I can tell the exact 15.925MHz is not at all critical.

[Mike Watterson]

Brilliant.
So, um, you have a stash of VERA tapes or some other 405 archives to convert? :D Or 405 cameras. But what's it for?

Though after a couple of demos the BBC scrapped VERA and bought Ampex gear. Probably easier to find working 405 Ampex than VERA HW.

[ppppenguin]

This is for use in the Broadcast Engineering Conservation Group where I am a trustee and treasurer.
https://becg.org.uk/

We want to be able to operate vintage cameras, possibly the whole "Vivat" OB truck at 405 while utilising the output at 625. BECG chairman Paul Marshall (and perhaps a few others) have working Quadruplex machines that can do 405. There are occasional 405 tapes on other formats, incluidng Sony CV2000. Though how my SAA7118 front end will cope with the rather non-standard signal from the CV2000 will have to await somebody turning up with a machine and tape.

[ppppenguin]

I've now done the SAA7118 clock geenration in the FPGA and it's OK.

The interpolation problem looks like odd and even fields getting swapped at the input to the framestore. Not surprised. The field sync arrangments definitely need work.

[`FRANK.C]

Hi Jeffrey
Well done that is truly amazing.
I would have never thought that reducing the clock speed would have worked so well.
The video decoder would be experting to see 625 or 525 lines per frame and when it doesn't I thought that it would complain.

I have noticed that the TVP5150 tries to make scene of a 405 signal. When a Hedghog is fed with a 405 signal it produces rubbish on the screen that varies with picture content.

Frank

[ppppenguin]

Frank, you could try this trick on the TVP5150 too. You'd need to feed 9.27818064MHz into the decoder instead of the 14.31818MHz xtal. Actual frequency isn't too critical, at least not on the SAA7118. You could go a few % either side without any trouble at all. As I said in an earlier post, I'm now using a DTO in the FPGA to generate the clock for the SAA7118. 16 bits was more than adequate. It's switchable between 405 and 625.

If you don't have a framestore, and hence a crystal for setting the output clock speed, you've got a have a crystal in the circuit somewhere. Otherwise the system will chase its own tail.

[`FRANK.C]

Hi Jeffrey
It should be easy enough to try on a Hedghog II as the 14.31818 MHz clock is produced from a PLL in the FPGA. I just checked the PLL will produce 9.272876 MHz
I guess the easiest way for me to view what the TVP5150 is producing is to separate the syncs and then send the output directly to the 405 side and view on a 405 TV.
When I get around to trying it I will let you know the results.

Frank

[`FRANK.C]

Hi Jeffrey
I gave it a quick lash up on a Hedghog II to see would the TVP5150 produce anything sensible.
I changed the video decoder clock to 9.272876 MHz.
I just separated the luminance and sent it directly across to the 405 side.
As the video clock from the decoder would be no longer 27 MHz I temporarily derived the 405 line clock from the 50 MHz clock.

I viewed the result on a 405 TV.

I cant believe it but the TVP5150 works!

The picture is floating horizontally and vertically as I haven't synced it at all but the result is very good
In the pictures below of the result the 405 video is supplied by another Hedghog. What is displayed is the 405 video straight out of the decoder and not converted to 625.
The first photo is the Hedghog test card. The second is test card C supplied from a Free view box. In the third picture the embedded syncs can be seen as two vertical lines.

Frank

[Mike Watterson]

Shows the value of informed experimentation. Excellent results.

I look forward to hearing more about how the OB / Scanner truck develops, Jeffery. I wonder what Frank will use this feature for?

Meanwhile I keep meaning to try a CB synth and a DSBSC mixer / Osc to see can use it for MW modulator. DC offset on the SA612 allows a carrier. The reference crystal is divided down for CB channels & I want close to 9kHz or 18kHz steps with a standard crystal.

The FPGA is handy when you have one in a project for more flexible choice of reference.

[Crackle]

Impressive work guys, but it is all way beyond my understanding.
Well done

Mike