17-06-2019, 06:20 AM
A discussion has arisen eslewhere about test signals in the vertical interval on 405.
The background to VITS (Vertical Interval Test Signals) is that they were used by broadcasters to monitor the transmission chain while programmes are being transmitted. A variety of signals have been used but "pulse and bar" was always included to check freuquecy and phase response. This give an immediate and accurate check by using a special graticule on a waveform monitor. Later systems such as the Tektronix 700 could make autpmatic measurements.
The vertical interval was later also used for teletext.
I don't know how much VITS was used on 405. Certainly the 405 and VITS eras didn't have any great overlap. by the time VITS was introduced 405 was very much a legacy service.
All vertical interval signals are a bit of a nuisance on 405 since many sets have poor vertical blanking. While it's entirely possible to put them on the 405 output of a converter (would need a little bit of spare logic in the FPGA, the actual design would be very simple) I would recommend against doing so. They don't have any sensible use outside a trasnmitter network and can cause visible artifacts.
The background to VITS (Vertical Interval Test Signals) is that they were used by broadcasters to monitor the transmission chain while programmes are being transmitted. A variety of signals have been used but "pulse and bar" was always included to check freuquecy and phase response. This give an immediate and accurate check by using a special graticule on a waveform monitor. Later systems such as the Tektronix 700 could make autpmatic measurements.
The vertical interval was later also used for teletext.
I don't know how much VITS was used on 405. Certainly the 405 and VITS eras didn't have any great overlap. by the time VITS was introduced 405 was very much a legacy service.
All vertical interval signals are a bit of a nuisance on 405 since many sets have poor vertical blanking. While it's entirely possible to put them on the 405 output of a converter (would need a little bit of spare logic in the FPGA, the actual design would be very simple) I would recommend against doing so. They don't have any sensible use outside a trasnmitter network and can cause visible artifacts.
www.borinsky.co.uk Jeffrey Borinsky www.becg.tv