A GPSDO frequency reference

[sreaves]

Jim,

I sent you a PM on the GPSDO project did you receive it?

Sam
W3OHM

[pab]

Dear jimmc101,

Thanks for sharing your project and experience, it's a very interesting one by the way.
I'm on my way to do something similar and I wonder if you would be so kind to answer me a couple of questions regarding PLL design:
1) How did you get to the (T)=N/(Ko+Kp) formula? The closest I could find was tau1=(Ko*Kp)/(N*wn^2) where wn=natural frequency.
2) Which simulation software did you use?

Greeetings,

PAB

[jimmc101]

The plus sign in your first equation is a typo it should be T =  N/(Kp*Ko).

The phase comparator converts a frequency error to phase and outputs a voltage which is a function of this error. (Charge pump type comparators excepted).
When the loop is in lock this corresponds to a pure integration with unit output scaled by some factor (Kp) this is equivalent to a integrator with a time constant of 1/Kp.
The VCO converts changes in this output and converts it into a change in frequency with a slope of (Ko) so now the time constant of the equivalent integrator is 1/(Kp*Ko).
Finally there is the frequency divider which reduces frequency changes from the VCO by a factor of N giving the time constant (T) of the equivalent integrator as N/(Kp*Ko).
I doesn't matter what units are used as long as they are consistant, I prefer to use Kp in volts/cycle and Ko in cycles per second per volt (Hz/V).  Purists use volts/radian and radians per second per volt.

The other equation puzzles me, wn = 1/T = (Ko*Kp)/N so the formula can be reduced to
tau1 = wn/wn^2 = 1/wn

Simulation
I'm old enough to have been taught analog computing back in the 1960s, so I use a simulation based on controlled voltage sources and integrators.

Using LTspice the simulation is as  below...

Open Loop Frequency Response
V1 Excitation V(AC)
1 volt Sinewave
B1 VCO V(df)=V(AC)*10
‘10’ Ko sensitivity in Hz/V
V(dF) Deviation from nominal frequency Hz
B2 Divider V= V(dF)/1000
‘1000’ N Division ratio
V(Fc) Output Hz
B3, 4, 5 Phase Comparator
B3 Integrator V(P)=idt(V(Fc))
Frequency to Phase conversion, Hz to cycles
B4 Inverter V(EX)=-V(P)
EXOR output, loop locks on negative slope
B5 Slope V(PHI)=V(EX)*10
‘10’ Kp slope in volts / Cycle, (EXOR supply voltage / 0.5)
Loop Filter ‘Real’ components

Closed Loop Frequency Response
As Open loop except…
B1 VCO V(dF)=(V(AC)+V(EFC))*10
‘10’ Ko sensitivity in Hz/V
V(dF) Deviation from nominal frequency Hz

Transient
B1 VCO V(dF)=(V(EFC)-2)*10
V(EFC) Control voltage
‘2’ Control voltage for nominal frequency
‘10’ Ko sensitivity in Hz/V, (EXOR supply voltage / 0.5)
V(dF) Deviation from nominal frequency Hz
B2 Divider V(Fc)= V(dF)/1000
‘1000’ N Division ratio
V(Fc) Output Hz
B3,4,5 Phase Comparator
B3 Frequency to Phase V(p)=idtmod(V(Fc),0.0,1,0)
Frequency to Phase conversion, Hz to cycles
0 to 1 cycle (EXOR repeats every cycle)
‘0.0’ Starting phase
V(P) Output cycles
B4 EXOR V=if((V(p)<0.5),V(P),(1-(V(P))))
Zero for Phase = 0 rising to 0.5 for Phase = 0.5 cycles     falling to Zero for Phase = 1 cycle
B5 Slope V(PHI)=V(EX)*10
‘10’ Kp slope in volts / Cycle, (EXOR supply voltage / 0.5)

Loop Filter ‘Real’ components
Initial voltage on capacitors, Half EXOR supply voltage
(Average EXOR output with square wave on one input only)


To be pedantic there should be a delay added within the loop equal to half the period of the comparison frequency to account for the effective sampling caused by phase information only being available at the edges of a square wave. For this loop this term is negligible.

I hope this is not too confusing.

Jim

Forgot to add the zip file contains the three LTspice simulations (.ASC files)