Measuring System A RF levels

[ppppenguin]

When working at the Vintage Wireless Museum we need to check RF signal levels. Terry Casey has kindly given us a suitable measurement set that covers VHF and UHF.  To measure a signal properly there must be a signficant amount of 100% carrier. In System I this is no problem as the sync tips are at 100%. For System A with +ve modulation it needs a significant amount of peak white in the video. Test card C or D is marginal so I've usually brought along a test pattern generator and set it to peak white full field. It would be useful to have this capability built into the converter rack so I've thought about different options.

I've got some ZNA134, ZNA234, SAA1043 and SAA1101 SPG chips. Any of these could do the job, simply connecting mixed sync and mixed blanking outputs via suitable resistors. Maybe a small cap to slow the rise times a bit. Today I realised I've already got suitable hardware. There's a CPLD (programmable logic device) in the control panel which I programmed to interface the buttons to the audio/video router. There's plenty of spare space in the device so I borrowed some VHDL from another project (my experimental 625 to 405 converter) and repurposed it as a simple mixed sync and mixed blanking generator.

Here's the first pass of the VHDL. Less than 100 lines including comments and blank lines. Totally untested but it synthesises OK and fits easily in the device. I'll try it out on a spare CPLD evaluation kit. I've calculated the 3 resistors needed but it will need a bit of AOT to get the levels absolutely correct.

Code:

-------------------------------- Peak White generator ---------------------------------------------------------------
-- Make MB and MS to be added via reistor network to make peak white
-- To give Thevenin equivalent of 2V, 75R: MB: 272R; MS: 635R; 0V: 124R

-- 25MHz has 1600 clocks per line, 800 per half line
-- Active line 52us = 1300ck; H blank  12us = 300ck; H sync 4.7us = 117ck; Front porch 1.6us = 40ck; Broad pulse 27.3us = 683ck
process (CK) begin
    if rising_edge(CK) then
    
-- Central H counter 0-799
        HRESET <= HCOUNT = 798;    -- Pipeline
        if HRESET then HCOUNT <= 0;
            else        HCOUNT <= HCOUNT + 1;
        end if;        

-- Half line toggle        
        if HRESET then HALF_LINE <= not HALF_LINE; end if;
        
-- Mixed sync. Line sync is in 1st half line
        MS_START <= (not EQ_EN and (HCOUNT = H_OFFSET) and not HALF_LINE)    -- Line sync on whole lines only
                         or (EQ_EN and (HCOUNT = H_OFFSET))                            -- EQ half lines in field interval
                         or (BP_EN and (HCOUNT = H_OFFSET));                        -- BP on half lines in field interval
        
        MS_END <= (not EQ_EN               and (HCOUNT = H_OFFSET + 254))        -- Sync pulses (4.7us)
                      or (EQ_EN and not BP_EN and (HCOUNT = H_OFFSET + 127))        -- EQ pulses (2.35us)
                      or (              BP_EN and (HCOUNT = H_OFFSET + 1474));    -- Broad pulses (27.3us)

        if     MS_START then MIXED_SYNC <= true;    -- JK flipflop
            elsif MS_END then MIXED_SYNC <= false;
            else              MIXED_SYNC <= MIXED_SYNC;
        end if;
        
-- H blanking (not quite full blanking as it doesn't encompass both sets of TRS)
        HBLANK_END <= HCOUNT = conv_std_logic_vector(566, 12);    -- ***** 567 i Misaligned by 1 clock but still works
        
        if       HRESET     then HBLANK <= true;    -- JK flipflop
            elsif HBLANK_END then HBLANK <= false;
            else                  HBLANK <= HBLANK;
        end if;
    
-- Mixed blanking
        MIXED_BLANKING <= HBLANK or VBLANK;
---------------------------

-- Central V counter
        if HRESET then    -- Count half lines
        
            VRESET <= VCOUNT = 623;
        
            if VRESET then VCOUNT <= 0;
                else        VCOUNT <= VCOUNT + 1 mod 1024;
            end if;

-- Odd/even field toggle
            if VRESET then HALF_FRAME <= not HALF_FRAME; end if;    -- Toggle every field            

-- Equalising pulses. 15 half lines
            EQ_EN_START <= VCOUNT = V_OFFSET + 3;            
            EQ_EN_END   <= VCOUNT = V_OFFSET + 18;
                                
            if       EQ_EN_START then EQ_EN <= true;    -- JK flipflop
                elsif EQ_EN_END   then EQ_EN <= false;
                else                   EQ_EN <= EQ_EN;
            end if;                

-- Broad pulses. 5 half lines
            BP_EN_START <= VCOUNT = V_OFFSET + 8;
            BP_EN_END   <= VCOUNT = V_OFFSET + 13;
                    
            if       BP_EN_START then BP_EN <= true;    -- JK flipflop
                elsif BP_EN_END   then BP_EN <= false;
                else                   BP_EN <= BP_EN;
            end if;

-- Vertical blanking
            VBLANK_START <= VCOUNT = V_OFFSET + 3;    -- First blanked: 623.5/311
            VBLANK_END <= VCOUNT = V_OFFSET + 53;    -- First active: 23.5/336

            if       VBLANK_START then VBLANK <= true;    -- JK flipflop
                elsif VBLANK_END   then VBLANK <= false;
                else                    VBLANK <= VBLANK;
            end if;                

        end if;    -- HRESET

    end if; -- CK
end process;

[ppppenguin]

I think I'll shrink down the full field white to a large white rectangle. A lot of older receivers don't much like full screen white, their EHT systems make a fuss.

In theory I could add things like crosshatch pattern and borrow some of the buttons to select them. Probably won't bother but nice to know it's possible. One of the great things about programmable logic.

BTW, the VHDL above has several whopping great errors to do with timings. Due to 54MHz clock on my 625>405 converter and 25MHz clock on the PLD board. I've tweaked them now. My view is to rough something together, try it and see what happens. Then I'll know pretty quickly if I'm doing something senible or not. Yes, I could simulate the VHDL design but I much prefer seeing traces on a scope.

[Terry]

I should point out that the analyser I've given to the museum, like the one I still have, is designed to scan the spectrum. This shows up problems such as spurii and ingress that a single channel measurement would miss.

My own meter will show the levels of up to four channels simultaneously, which is even better!

The point is that, because of the scanning process, each channel is only sampled for a brief period which is fine with negative modulation because there is a 100% modulation sync pulse every 64µS whereas, on normal programme material, a positive modulation signal might have 100% peak white signals once in a while. Even a test card has very little peak white in it, if you look closely.