12-02-2016, 10:08 AM
Made a tweak to the VHDL. At power up all registers initialise to logic 0 unless otherwse specified. This is fine for the registers that hold the values for Preview and BBC1 as this source is BBC1 off air. However the ITV and BBC2 registers also initialise to BBC1 off air. I added explicit initialisation to all 4 registers.
signal SELECTED_OUTPUT0 : std_logic_vector(3 downto 0) := "0000";
signal SELECTED_OUTPUT1 : std_logic_vector(3 downto 0) := "0001";
signal SELECTED_OUTPUT2 : std_logic_vector(3 downto 0) := "0010";
signal SELECTED_OUTPUT3 : std_logic_vector(3 downto 0) := "0000";
Wouldn't have been so easy in a hardware design. Would have needed to fit inverters before and after the relevant registers.
I pondered including an "Easter Egg". https://en.wikipedia.org/wiki/Easter_egg_%28media%29 But couldn't work up the enthusiasm to do it. My Tektronix 1755A vectorscope has an Easter Egg. Pressingthe right combination of buttons will give a screen full of fish swimming around.
signal SELECTED_OUTPUT0 : std_logic_vector(3 downto 0) := "0000";
signal SELECTED_OUTPUT1 : std_logic_vector(3 downto 0) := "0001";
signal SELECTED_OUTPUT2 : std_logic_vector(3 downto 0) := "0010";
signal SELECTED_OUTPUT3 : std_logic_vector(3 downto 0) := "0000";
Wouldn't have been so easy in a hardware design. Would have needed to fit inverters before and after the relevant registers.
I pondered including an "Easter Egg". https://en.wikipedia.org/wiki/Easter_egg_%28media%29 But couldn't work up the enthusiasm to do it. My Tektronix 1755A vectorscope has an Easter Egg. Pressingthe right combination of buttons will give a screen full of fish swimming around.
www.borinsky.co.uk Jeffrey Borinsky www.becg.tv