Lattice iCE40HX1K FPGA

[ppppenguin]

I meant both. The Picoblaze is tiny. Even an 8051 class MPU isn't very big relative to a medium or large FPGA. If you want RAM and/or program storage on the FPGA that uses a lot of block RAM.

[`FRANK.C]

I have fitted a 405 line test card into a programming image. The test card and the sync generation for it was much larger than the converter.
I had to whittle a good bit of it away to make it fit.

I also had a bit of a play with the cold boot. It works very well.
The PIC sequences the selection of the image and the resetting of the FPGA.
The cold boot will be useful and will allow the test card to be used.

One thing that struck me was how small the programming file for the iCE40HX1K is compared to others.
The programming file for the EP4CE6E that is used in the Hedghog II is 2 MB
The file for the EP2C5 used in the Hedghog is 512 KB
The file for the iCE40HX1K is a just 32KB

Frank

[ppppenguin]

I assume you're comparing like with like here for file sizes. That is raw binary, not any other format.

I suspect a lot of a FPGA config file is for presetting the contents of block RAM. If the device doesn't have block RAM or it can't be preset, then that all goes away.

[`FRANK.C]

Hi Jeffrey
I was looking at the files I used to program each.
But they are different types.
The files for the Cyclones are .jic programmed using the JTAG port.
While the iCE40HX1k file is .bin programmed via SPI interface.

Looking at the EP4CE6E the original output file which is a .sof is 351 KB. Which considering the size of the EP4CE6E is more comparable with the iCE40HX1k file.
It is only after conversion it bloats out to 2049 KB. This looks like an incredible increase in size. As far as I know it contains nothing extra apart for the bootloader for the flash memory.

Frank

[`FRANK.C]

I have spent some more time on this.
The time redistribution memory was inferred and wouldn't synthesize as I wanted. Only the write clock was connected to the BRAM. The read clock only connecting to some registers on the output from the memory.
This I could see on the RTL viewer.

I spent a lot of time fruitlessly trying to get the Memory building tool working and eventually had to give up.
The only option that I could see was to use primitives. I hadn't used them before so it took a while to get to grips with them.
But I got the memory built with them and it now synthesizes as I want.

Frank

[ppppenguin]

Synthesising memory can be a bit of a black art. I only know the tricks for Xilinx but other makes may be similar. For small memories that will be implemented in the logic cells it's easy.  There are common constructs that will synthesise memory. When reading memory, if the read address generator gives you an SLV you will need to cast it to INTEGER to give the read address.

If you want to use block memory I would normally declare it using the primitive. Or alternatively use whatever tools are available to build it as a component. This latter approach works well if you want a memory that needs multiple block RAMs.

Here's a 2Kx9 dual port using a single RAM. Declaration and then instatiation. The RAM was built with Xilinx tools and declared as a component.

Code:

-- CD400 BRAM for sync and burst edges. Single BRAM, both ports 2K*9. Latency = 1
component sync_burst_edge_ram port (
    clka, clkb : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    addra, addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
    doutb : OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
end component;

EDGE_RAM_CD400 : sync_burst_edge_ram port map (
        CLKA => CKC, DINA => CONTROL_DATA(8 downto 0), ADDRA => RAM_WADDR(10 downto 0), WEA(0) => RAM_WRITE,
        CLKB => CK, ADDRB => SYNC_RAM_ADDR(10 downto 0), DOUTB => SYNC_LUT_CD400);

Here's a big RAM that used 6 BRAM blocks

Code:

-- 6xBRAM (32768x3) for ident generator
component kram32768x3 port (
    clka, ena, clkb, enb : IN std_logic; wea: IN std_logic_VECTOR(0 downto 0);
    addra, addrb: IN std_logic_VECTOR(14 downto 0);
    dina: IN std_logic_VECTOR(2 downto 0);    doutb: OUT std_logic_VECTOR(2 downto 0));    
end component;

IDENT_RAM1 : KRAM32768X3 PORT MAP (
    CLKA => CKC, ENA => '1', WEA(0) => RAM_WRITE, ADDRA => RAM_WADDR, DINA => CD(2 downto 0),    
    CLKB => CK, ENB => CE, ADDRB => std_logic_vector(RAM_READ_ADDRESS(14 downto 0)),    -- Remove sign bit and convert to SLV    
    DOUTB => IDENT_RAM_DATA);

Having to declare the write enables (WEA) as 1 bit SLV rather than std_logic is a quirk of the Xilinx memory generator.

[ppppenguin]

Adding an example of inferred memory. This is only 1 bit wide. For multibit memory you need a 2 dimensional array.

Code:

Signal declarations for 192x1 dual port RAM. 1st port is write only, 2nd port is read only. I could equally have done this with the memory generation tools but it was simpler and more logical to infer it.

-- C status memory and loader
signal C_STATUS_BIT : std_logic;
signal C_STATUS_BITS : std_logic_vector(15 downto 0);
signal RAM_WADDR : std_logic_vector(7 downto 0);
-- DPRAM 192x1
type DPRAM192x1 is array(191 downto 0) of std_logic;
signal CSTAT_RAM_MAIN, CSTAT_RAM_DARS : DPRAM192x1;

Write address. Note cast to integer
if (CONTROL_ADDRESS(19 downto 8) = X"500") and CWRA = '1' then CSTAT_RAM_MAIN(conv_integer(CONTROL_ADDRESS(7 downto 0))) <= CONTROL_DATA(0); end if;

Read address. Again note cast to integer
C_STATUS_BIT <= CSTAT_RAM_MAIN(conv_integer(AUDIO_FRAME));

[`FRANK.C]

Hi Jeffrey
Having to declare the write enables as 1 bit SLV is one of those things that if you know it isn't a problem but if you don't you could spend hours tearing your hair out.

What I am using now for the time redistribution fifo is below.
The BRAM is in 4k blocks and SB_RAM2048x2 is a privative foe 2048 X 2 RAM. It appears to  synthesize  and work ok.

Code:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

library work;
use vcomponent_vital_2.all;

entity fifo_tr is

port (
    wrreq : in std_logic;
    rdreq : in std_logic;
    aclr  : in std_logic;
    rdclk : in std_logic;
    wrclk : in std_logic;
    data     : in std_logic_vector (7 downto 0);      -- data in
    q         : out std_logic_vector (7 downto 0));    -- data out
end fifo_tr;


architecture rtl of fifo_tr is

signal WR_ADD         : std_logic_vector(10 downto 0);
signal RD_ADD         : std_logic_vector(10 downto 0);
signal DATAin1     : std_logic_vector(1 downto 0);
signal DATAin2     : std_logic_vector(1 downto 0);
signal DATAin3     : std_logic_vector(1 downto 0);
signal DATAin4     : std_logic_vector(1 downto 0);
signal DATAout1     : std_logic_vector(1 downto 0);
signal DATAout2     : std_logic_vector(1 downto 0);
signal DATAout3     : std_logic_vector(1 downto 0);
signal DATAout4     : std_logic_vector(1 downto 0);

signal ACLR_B         : std_logic;
signal ACLR_C         : std_logic;

begin

u1 : SB_RAM2048x2 port map ( RDATA => DATAout1, RADDR => RD_ADD, RCLK => rdclk, RCLKE => '1', RE => '1', WADDR => WR_ADD,
            WCLK=> wrclk, WCLKE => '1', WDATA => DATAin1, WE => wrreq );

u2 : SB_RAM2048x2 port map ( RDATA => DATAout2, RADDR => RD_ADD, RCLK => rdclk, RCLKE => '1', RE => '1', WADDR => WR_ADD,
            WCLK=> wrclk, WCLKE => '1', WDATA => DATAin2, WE => wrreq );

u3 : SB_RAM2048x2 port map ( RDATA => DATAout3, RADDR => RD_ADD, RCLK => rdclk, RCLKE => '1', RE => '1', WADDR => WR_ADD,
            WCLK=> wrclk, WCLKE => '1', WDATA => DATAin3, WE => wrreq );

u4 : SB_RAM2048x2 port map ( RDATA => DATAout4, RADDR => RD_ADD, RCLK => rdclk, RCLKE => '1', RE => '1', WADDR => WR_ADD,
            WCLK=> wrclk, WCLKE => '1', WDATA => DATAin4, WE => wrreq );

-------------------------------------------------------------------------------------------------
------------------------------------ processes --------------------------------------------------
-------------------------------------------------------------------------------------------------     
    process (wrclk)
    begin
        if rising_edge(wrclk) then
            
            DATAin1 <= data(1 downto 0);
            DATAin2 <= data(3 downto 2);
            DATAin3 <= data(5 downto 4);
            DATAin4 <= data(7 downto 6);
            
            if aclr = '1' then
                WR_ADD <= "00000000000";
            else
                if (wrreq = '1') then
                    WR_ADD <= WR_ADD + '1';
                end if;
            end if;
        end if;
    end process; --wrclk
    
        
    process (ACLR_C, aclr)
    begin  
        if ACLR_C = '1' then ACLR_B <= '0';  
        elsif rising_edge(aclr) then ACLR_B <= '1';  
        end if;
    end process; --ACLR_C, aclr
        
        
    process (rdclk)
    begin
        if rising_edge(rdclk)  then
                if (rdreq = '1') then
                    RD_ADD <= RD_ADD + '1';
                    if ACLR_B = '1' then
                        ACLR_C <= '1';
                        RD_ADD <= "00000000000";
                    else
                        ACLR_C <= '0';
                    end if;
                end if;
            
                q(1 downto 0) <= DATAout1;
                q(3 downto 2) <= DATAout2;
                q(5 downto 4) <= DATAout3;
                q(7 downto 6) <= DATAout4;
                
        end if;
    end process; --rdclk
end rtl;

Another thing I noticed on the RTL viewer and also on the technology view was that the registers on the input and output pins were not been used. The signals passed through them without any clock.
As far as I understand they should be used by default. I can put them working by using primitives.

Frank