Lattice iCE40HX1K FPGA

[ppppenguin]

Adding an example of inferred memory. This is only 1 bit wide. For multibit memory you need a 2 dimensional array.

Code:

Signal declarations for 192x1 dual port RAM. 1st port is write only, 2nd port is read only. I could equally have done this with the memory generation tools but it was simpler and more logical to infer it.

-- C status memory and loader
signal C_STATUS_BIT : std_logic;
signal C_STATUS_BITS : std_logic_vector(15 downto 0);
signal RAM_WADDR : std_logic_vector(7 downto 0);
-- DPRAM 192x1
type DPRAM192x1 is array(191 downto 0) of std_logic;
signal CSTAT_RAM_MAIN, CSTAT_RAM_DARS : DPRAM192x1;

Write address. Note cast to integer
if (CONTROL_ADDRESS(19 downto 8) = X"500") and CWRA = '1' then CSTAT_RAM_MAIN(conv_integer(CONTROL_ADDRESS(7 downto 0))) <= CONTROL_DATA(0); end if;

Read address. Again note cast to integer
C_STATUS_BIT <= CSTAT_RAM_MAIN(conv_integer(AUDIO_FRAME));