14-05-2020, 03:05 PM
Care is needed when crossing between clock domains. The SDRAM and its controller runs at 108MHz in my converter. Not critical, it just had to be high enough to give enough memory bandwidth, and below the 133MHz limit of the SDRAM I was using. All the request/grant is done with standard duall flipflop pulse synchronisers. One critical factor is the length of block that you read or write with each request. Each block read or write has an overhead when setting it up. Up to a point, longer blocks give greater BW but less flexibility. There are subtle ways of overlapping block operations slightly but I've avoided doing that as it's a bit hairy.
If you use SRAM rather than DRAM the multiplex principles are the same. You still need a request/grant system. But there's less overhead when switching between ports and no need for refresh. Also no startup sequence. I'll send you the VHDL (though I think you've already got it) and the spreadsheet that I use to analyse the timing.
If you use SRAM rather than DRAM the multiplex principles are the same. You still need a request/grant system. But there's less overhead when switching between ports and no need for refresh. Also no startup sequence. I'll send you the VHDL (though I think you've already got it) and the spreadsheet that I use to analyse the timing.
www.borinsky.co.uk Jeffrey Borinsky www.becg.tv
