14-05-2020, 08:48 AM
If using AL422 class serial framestores you can frig multiple ports to some extent. Let's say you want a 4 line interpolator. Use 4 framestores, each fed by the input delayed by 1,2,3 lines. Or you can interpolate before the framestore. The fun comes if you want to go flexibly both up and down in line number. Either you have to move the interpolator between input and output, use multiple framestores or use mutliple access like I did.
Because I'd synthesised multiport access on SDRAM for a number of professional projects I took that approach. It took a lot of work to develop the ideas and get them to work reliably, especially if I was pushing the memory bandwidth right up to the limit. My experimental 625 to 405 converter was actually a very easy memory job compared to some I've done.
My multiport stuff uses fixed round robin sequencing of ports, along with request/grant logic for each slot in the sequence. You always need some form of request/grant but in theory you can get slightly more bandwidth by granting slots as soon as possible rather than in round robin fashion. However it's more complex and not 100% deterministic. I wasn't prepard to get into a design that had statistical failure modes that might happen once in a blue moon.
Frank, you're very welcome to all my VHDL for this. It's for original SDRAM and would need a fair bit of modification for later memory such as DDR3. The basic concepts don't change but there's a lot of detail. Xilinx now offer cores for multiport DRAM access. Altera may do likewise. I havn't looked at them seriously.
Because I'd synthesised multiport access on SDRAM for a number of professional projects I took that approach. It took a lot of work to develop the ideas and get them to work reliably, especially if I was pushing the memory bandwidth right up to the limit. My experimental 625 to 405 converter was actually a very easy memory job compared to some I've done.
My multiport stuff uses fixed round robin sequencing of ports, along with request/grant logic for each slot in the sequence. You always need some form of request/grant but in theory you can get slightly more bandwidth by granting slots as soon as possible rather than in round robin fashion. However it's more complex and not 100% deterministic. I wasn't prepard to get into a design that had statistical failure modes that might happen once in a blue moon.
Frank, you're very welcome to all my VHDL for this. It's for original SDRAM and would need a fair bit of modification for later memory such as DDR3. The basic concepts don't change but there's a lot of detail. Xilinx now offer cores for multiport DRAM access. Altera may do likewise. I havn't looked at them seriously.
www.borinsky.co.uk Jeffrey Borinsky www.becg.tv
