15-08-2019, 09:10 AM
The registers that play with vertical timing aren't any use. The fundamental V and F sync separation just doesn't work well on 405. There's a plausible looking V sync pulse. Alternate pulses are in the right place and somewhere totally wrong. I could cope with that and gate out the unwanted pulse. Except that when you disconnect and reconnect the 405 input it's random whether the good pulse is on the odd or even field. I can't see any way at present of reliably discriminating between odd and even fields by purely logical means.
That leaves passing raw ADC data to the FPGA or using a LM1881.
That leaves passing raw ADC data to the FPGA or using a LM1881.
www.borinsky.co.uk Jeffrey Borinsky www.becg.tv
