10-08-2019, 05:55 AM
The clock input to the decoder is being made with a DTO so there is an inherent jitter of one cycle of the master clock. In my work the master clock is 108MHz and the feed to the decoder is about 16MHz. The jitter is about 9ns. I haven't looked at the clock out of the decoder. This may or may not suffer from the same jitter but it doesn't matter on my design because of the framestore.
Actually there may well be jitter in the sampling of the 405 input but at 9ns this won't be visible. When I was doing 625 to 405 conversion I made the output lock with a DTO and this also had 9ns jitter. Again entirely invisible.
Actually there may well be jitter in the sampling of the 405 input but at 9ns this won't be visible. When I was doing 625 to 405 conversion I made the output lock with a DTO and this also had 9ns jitter. Again entirely invisible.
www.borinsky.co.uk Jeffrey Borinsky www.becg.tv
