19-02-2019, 09:07 AM
(This post was last modified: 19-02-2019, 09:15 AM by ppppenguin.)
In a FPGA unused pins are more or less floating. On a Xilinx they have a weak pull-up and Altera is probably similar. So the usual arrangement is to leave them open circuit on the PCB. No harm in connecting them to 0V. They don't need to be explicity specified. In older Xilinx software the pinouts and much else is specified in a UCF file. Here's an example pin called pSEP_MS wich is allocated to pin R24. I have also declared to be 3.3V CMOS though this could have been done globally in the design.
NET "pSEP_MS" LOC = R24 |IOSTANDARD = "LVCMOS33" ;
There must be a similar file in the Altera software.
In some very high speed designs it's recommended to ground unused pins and possibly force them to logic 0. This is to reduce ground bounce. This is definitely NOT a problem on Hedghog.
I've looked at the MegaWizard plug-in manager and it's Altera's equivalent of Xilinx Coregen.
NET "pSEP_MS" LOC = R24 |IOSTANDARD = "LVCMOS33" ;
There must be a similar file in the Altera software.
In some very high speed designs it's recommended to ground unused pins and possibly force them to logic 0. This is to reduce ground bounce. This is definitely NOT a problem on Hedghog.
I've looked at the MegaWizard plug-in manager and it's Altera's equivalent of Xilinx Coregen.
www.borinsky.co.uk Jeffrey Borinsky www.becg.tv
