Building a Standards Converter

[ppppenguin]

Looks like development is going nicely. I had a very quick look at some of the VHDL. This line could be a liability:

Code:

    VIDEO_SUMMED <= VIDEO_MULT_A + VIDEO_MULT_B + VIDEO_MULT_C + VIDEO_MULT_D + VIDEO_MULT_E + VIDEO_MULT_F ;

The clock speed is pretty low so it should work but it's a potential trouble spot in getting the design to meet its timing specs. Unless I had a very good reason not to I would always pipeline this sort of adder:


PARTIAL_SUM1 <= VIDEO_MULT_A + VIDEO_MULT_B;
PARTIAL_SUM2 <= VIDEO_MULT_C + VIDEO_MULT_D;
PARTIAL_SUM3 <= VIDEO_MULT_E + VIDEO_MULT_F;

VIDEO_SUMMED <= PARTIAL_SUM1 + PARTIAL_SUM2 + PARTIAL_SUM3;

Other signals may need to be pipelined to match this extra delay. The extra registers in the adder are a free resource as they are part of the logic cell and not being used.

If it's got to go really fast then the final sum could be split into 2 stages but that's normally for speeds much higher than used in Hedghog.