04-01-2019, 05:48 PM
That MJH converter is a new one to me. I suppose I should have known about it but it eluded me. Fom Andy's description it doesn't sound very well designed. The principle of using a dual port RAM with counters each side for 625 and 405 is fair enough. As is the use of standard ADC and DAC parts. The main memory is a 1Kx8 dual port RAM. I've dug out the data sheet and attached the first page.
From Andy's description, it looks like there was no attempt to lock the input sampling clock to the signal. This will work but give slightly ragged verticals. Actually it is possible to use an async sampling clock. Techwell (now Intersil) did a range of PAL/NTSC decoders that used a fixed 27MHz sample clock. This was followed by a fairly complex digital interpolator to align the async samples to a fixed grid. The results were very good. I used one of their parts in a professional design that was used in security video applications.
I should add that all the commercial designs I mentioned gave very good results. The Pineapple suffered minor niggles but was pretty good. The Domino had limited bandwidth due to a rather low sampling frequency. The others were verging on faultless.
From Andy's description, it looks like there was no attempt to lock the input sampling clock to the signal. This will work but give slightly ragged verticals. Actually it is possible to use an async sampling clock. Techwell (now Intersil) did a range of PAL/NTSC decoders that used a fixed 27MHz sample clock. This was followed by a fairly complex digital interpolator to align the async samples to a fixed grid. The results were very good. I used one of their parts in a professional design that was used in security video applications.
I should add that all the commercial designs I mentioned gave very good results. The Pineapple suffered minor niggles but was pretty good. The Domino had limited bandwidth due to a rather low sampling frequency. The others were verging on faultless.
www.borinsky.co.uk Jeffrey Borinsky www.becg.tv
