19-09-2018, 08:46 AM
(This post was last modified: 19-09-2018, 09:00 AM by ppppenguin.)
Peter, I'd forgotten you'd built a Darius converter. His design was clever but flawed. The video bandwidth was limited by the CCD analogue delays and the logic design was, to put it charitably, mediocre. On the other hand I believe his modulator was excellent though I've not had a chance to measure one.
If you're playing with different timings for 405 input then you really want programmable logic. A Domino or Dinosaur might be quite a good candidate as a starting point, pull out the main logic and put in an FPGA. But if you had either of these would you really want to chop it about?
If I was building a 405 front end for my own experimental 625 to 405 converter, I'd use a TD8708 or TDA8709 ADC and one of the common sync separator chips. The PLL could be a HC4046, discrete (as in Dinosaur) or in the FPGA. I might well run the whole converter at 2x or 4x oversampled to minimise filter requirements. The extra storage and hgher logic speeds should be no problem for the memory and FPGA.
Incidentally, I think the Dinosaur's clock generator and PLL was based on the BBC CO6/509. I have the relevant schematics (of most of the converters that have been built) but I'd need permission from the designers of Dinosaur and Domino to post them in a public forum. I've posted fragments of the Aurora schematics but wouldn't post the whole thing without permission from Darryl. The Hedghog (and Darius's design) are freely available.
If you're playing with different timings for 405 input then you really want programmable logic. A Domino or Dinosaur might be quite a good candidate as a starting point, pull out the main logic and put in an FPGA. But if you had either of these would you really want to chop it about?
If I was building a 405 front end for my own experimental 625 to 405 converter, I'd use a TD8708 or TDA8709 ADC and one of the common sync separator chips. The PLL could be a HC4046, discrete (as in Dinosaur) or in the FPGA. I might well run the whole converter at 2x or 4x oversampled to minimise filter requirements. The extra storage and hgher logic speeds should be no problem for the memory and FPGA.
Incidentally, I think the Dinosaur's clock generator and PLL was based on the BBC CO6/509. I have the relevant schematics (of most of the converters that have been built) but I'd need permission from the designers of Dinosaur and Domino to post them in a public forum. I've posted fragments of the Aurora schematics but wouldn't post the whole thing without permission from Darryl. The Hedghog (and Darius's design) are freely available.
www.borinsky.co.uk Jeffrey Borinsky www.becg.tv
