Building a Standards Converter

[ppppenguin]

The 2 main questions with a 405>625 converter are coping with imperfect sources and input filtering. If the input sampling is at around 9MHz the conversion to 625 is simple but you need a very good input filter to avoid aliasing. Alternatively you can oversample (2x or 4x) which gives a simple input filter but needs a decimating filter in the FPGA. I've designed a precision upsampling filter which uses a LOT of multipliers (161 taps, 23 multipliers) but we don't need that level of performance. There's a tradeoff between complexity and performance. I have no instinctive feel for where the sweet spot might lie. Once you have the filter coefficients then the Xilinx Coregen tools will implement the filter without difficulty.

Another approach is conceptually very simple. Keep the oversampled signal throughout the converter. Accept the increased processsing speeds and memory usage. The output is then nicely oversampled too, making the post-DAC filter very easy.

The input arrangements would normally be done by phaselocking a clock to the incoming syncs. An alternative approach would be to used a fixed sampling clock, find the sync edges and resample in digits. I know this is done in the Techwell decoder chips and works well. I don't know how complex the correlation and resampling logic will be. the correlator finds the sync edges. The resampler interpolates the input samples on to an orthogonal grid.