11-02-2018, 06:06 AM
(10-02-2018, 05:46 PM)`FRANK.C Wrote:The truth is, though it looks neater, it makes precious little difference to the final generated code (assume the compiler is a decent one) as the code fit should treat both those statements the same.(10-02-2018, 08:01 AM)ppppenguin Wrote: Frank, boolean type is almost essential in VHDL. Whenever you say something like B <= (S = X"25"); then B is boolean.
Hi Jeffery
For something like that I would currently write
if S = x"25" then B <= '1' else B <= '0';
I do this without even thinking, its the microcontroller programing creeping in.
Writing it proper using Boolean is much clearer and easier to read back.
Coding style is as much an art as it is science. What is critical is getting the architecture right AT THE START - the implementation style can impact code size and efficiency, but a broken architecture is death for the project.
Where coding style IS important is when others are also working on/maintaining the code - a consistent style is absolutely vital if a third party needs to understand it, as is documentation and sensible in-line commenting.
I always comment code, especially when non-obvious decisions are made as if I return to something complex years later (e.g. to modify the code for a different platform), the design rationale may have been long forgotten...
One system you might want to look at is JavaDoc/Doxygen where tags in the comments allow you to generate a software architecture web site automatically - Doxygen is freely available and is very widely used in professional circles.
It supports VHDL out of the box - just running it even on non-marked-up code will generate a web site that details all your routines, their parameters, the calling tree etc. Very easy to use and incredibly useful - whenever I'm presented with someone's code, the first thing I do is run Doxygen over it, then browse the generated architecture diagrams. Have a play.
EDIT: There is a branch of Doxygen with built-in Verilog support at: https://github.com/avelure/doxygen-verilog
sıʌǝɹq ɐʇıʌ `ɐƃuol sɹɐ
ʞɔıu
ʞɔıu







