02-09-2017, 12:25 PM
Just a quick up date on what has been happening with this project.
I been trying to get Rf out of the FPGA. I have tried to get it via the R2R ladder but any attempt to use the ladder has resulted in severe pixellation, with 4 or 5 of the least significant bits out of the 9 in total having no effect. I think this is most lightly due to the 45 MHz carrier being above the maximum frequency of the ladder. I have looked on line to find the maximum frequency of R2R ladders but couldn't find any reference to it anywhere, not even in the data sheets of R2R ladder networks. I guess I could use a high speed DAC chip but I don't want to go down that route. The only way that I could get a watchable picture was to put a emitter follower on the output of the R2R ladder and connect the emitter of the emitter follower via a resistor to a pin of the FPGA. This pin of the FPGA is configured as open collector and is driven with the RF carrier. The result is modulated RF at this pin. A sketch of the basic circuit is attached below and also a photo of the results on screen. It is watchable but there is an underlying amount of noise which makes the picture somewhat murky. The noise is coming from the FPGA pin and can clearly be seen on a scope if the pin is connected to VCC via a resistor.
Cleaning up the noise would probably result in a good picture but I have decided to leave my attempts of getting RF from the FPGA at that and go down the MC44BS373 route. One of the reasons is that I could use the cheaper Cyclone II board which I am now using. When changing to the Cyclone II I took the opportunity to tidy up the files. I had a number of small files all connected through the top level file, resulting in the top level file being a pure rats nest of wiring. I merged a lot of the files together and connected the remaining files in a more streamlined fashion, this has made navigating the files easier.
Frank
I been trying to get Rf out of the FPGA. I have tried to get it via the R2R ladder but any attempt to use the ladder has resulted in severe pixellation, with 4 or 5 of the least significant bits out of the 9 in total having no effect. I think this is most lightly due to the 45 MHz carrier being above the maximum frequency of the ladder. I have looked on line to find the maximum frequency of R2R ladders but couldn't find any reference to it anywhere, not even in the data sheets of R2R ladder networks. I guess I could use a high speed DAC chip but I don't want to go down that route. The only way that I could get a watchable picture was to put a emitter follower on the output of the R2R ladder and connect the emitter of the emitter follower via a resistor to a pin of the FPGA. This pin of the FPGA is configured as open collector and is driven with the RF carrier. The result is modulated RF at this pin. A sketch of the basic circuit is attached below and also a photo of the results on screen. It is watchable but there is an underlying amount of noise which makes the picture somewhat murky. The noise is coming from the FPGA pin and can clearly be seen on a scope if the pin is connected to VCC via a resistor.
Cleaning up the noise would probably result in a good picture but I have decided to leave my attempts of getting RF from the FPGA at that and go down the MC44BS373 route. One of the reasons is that I could use the cheaper Cyclone II board which I am now using. When changing to the Cyclone II I took the opportunity to tidy up the files. I had a number of small files all connected through the top level file, resulting in the top level file being a pure rats nest of wiring. I merged a lot of the files together and connected the remaining files in a more streamlined fashion, this has made navigating the files easier.
Frank
