Building a Standards Converter

[ppppenguin]

All FPGAs have their little quirks and annoyances. They usually come and bite you when you're least expecting them. For Xilinx Spartan 3 series the quirks have mainly been in clock distribution, not helped by the tools sometimes making strange decisions on how to allocate the global and regional clock buffers. However some things are unexpectedly trouble free. I thought I'd have hell to pay when I made a 49.152MHz clock from 148.5MHz. Why 49.152MHz? It's a convenient multiple (1024) of the 48kHz AES audio sampling frequency. Allows me enough clock cycles (32) per audio bit to do all the processing while being low enough to be like DC for the FPGA. 98.304MHz would have been a bit fast for convenience while 24.576MHz would have been marginal for doing all the processing.

148.5MHz was the main crystal oscillator, it's the pixel clock for 1080/50p etc HDTV. The Xilinx Spartan 3A PLLS can do a maximum of 32 on both numerator and denominator. So going to 54MHz for standard definition related stuff is no problem, it's just 4/11. Getting from there to 49.152MHz takes 3 steps.

Multiply by 32/9 to get 192MHz
Divide by 5 to 38.4MHz (ordinary logic for once, no PLL)
Multiply by 32/25.

I couldn't find a simpler way, even if I started from 148.5MHz rather than 54MHz.

All worked immaculately at first attempt. Including nice low jitter. Been an utterly trouble free part of the design.