19-03-2017, 08:40 PM
I got some time over the weekend to have a play and decided to install the FPGA in place of the CPLD. The headers on the two boards are different so a bit of rewiring was needed. The first photo below shows the CPLD on the left and the FPGA on the right. The second photo shows the FPGA installed.
I reconfigured the files to suit the FPGA and programmed it, but there was no output. A few checks showed that there was plenty of life on the write side but no activity on the read side. The read clock was taken from the driven side of the 9 MHz microcontroller crystal and is of low amplitude, not much over a volt. I got away with using it with the CPLD but it wasn’t good enough to drive the FPGA.
I though that this would be a good opportunity to try a DTO that Jeffrey had explained.
There is an on board 50 MHz clock which I used. Then I basically copied the relevant parts from Jeffrey's file to give a 9 MHz output frequency and it worked. I used it to clock the microcontroller as well.
The output was a bit jittery due to the low (50 MHz) clock but it gave a watchable picture.
Today I found the PLL function on the FPGA and configured it to give a X3 output giving a 150 MHz clock. I rewrote the file to suit and now the 9 MHz clock is much more stable. A DTO is extremely useful. Thanks again Jeffrey for explaining it.
Frank
I reconfigured the files to suit the FPGA and programmed it, but there was no output. A few checks showed that there was plenty of life on the write side but no activity on the read side. The read clock was taken from the driven side of the 9 MHz microcontroller crystal and is of low amplitude, not much over a volt. I got away with using it with the CPLD but it wasn’t good enough to drive the FPGA.
I though that this would be a good opportunity to try a DTO that Jeffrey had explained.
There is an on board 50 MHz clock which I used. Then I basically copied the relevant parts from Jeffrey's file to give a 9 MHz output frequency and it worked. I used it to clock the microcontroller as well.
The output was a bit jittery due to the low (50 MHz) clock but it gave a watchable picture.
Today I found the PLL function on the FPGA and configured it to give a X3 output giving a 150 MHz clock. I rewrote the file to suit and now the 9 MHz clock is much more stable. A DTO is extremely useful. Thanks again Jeffrey for explaining it.
Frank
