Building a Standards Converter

[ppppenguin]

Frank, your comment about processes executing in parallel is a good one. Just because VHDL looks a bit like a procedural computer language (like C or BASIC) doesn't mean that it is one. VHDL and Verilog are primarily hardware description languages. Fortuantely for me I think mainly in hardware rather than software so it comes naturally. On the odd occasions I'm writing procedural software I have to remember the difference.