12-03-2017, 09:18 PM
Glad to see you've given yourself more programmable resources to play with. I've done more than enough of trying to cram a design into a device that's only marginally big enough. Not fun. Usually happens when the client wants extra functions added to an existing product.
VHDL is definitely the way to go. Or Verilog if you prefer, but I've not studied that at all. It alows you to concentrate on the logic of what you're trying to do rather than piece together a schematic of so-called standard parts.
The attached file is incredibly useful. It was given to me by a friendly engineer. You can use it as part of a project or simply take the VHDL from it an use it as part of another module. There are many occasions when you will need to convert between boolean and std_logic. Any comparison result is inherently boolean so if you want to use that result as a simple std_logic you need this function.
For example comparing a pair of std_logic_vectors and converting the result to std_logic:
my_std_logic_signal <= to_std_logic(slv1 > slv2);
The other way round, std_logic to boolean is most easily done inline as you need it:
my_boolean <= (my_std_logic = '1');
You've already found that conditional functions such as "if" must have a boolean argument. It's often OK to write things such as:
if CARRY = '1' then COUNT <= COUNT + 1;
end if;
But if CARRY is a boolean type
if CARRY then COUNT <= COUNT + 1;
end if;
A reminder that boolean signals can only take 2 values: true or false. As against std_logic whch usually takes the values 0 or 1. Though it can take others such as U (undefined).
VHDL is definitely the way to go. Or Verilog if you prefer, but I've not studied that at all. It alows you to concentrate on the logic of what you're trying to do rather than piece together a schematic of so-called standard parts.
The attached file is incredibly useful. It was given to me by a friendly engineer. You can use it as part of a project or simply take the VHDL from it an use it as part of another module. There are many occasions when you will need to convert between boolean and std_logic. Any comparison result is inherently boolean so if you want to use that result as a simple std_logic you need this function.
For example comparing a pair of std_logic_vectors and converting the result to std_logic:
my_std_logic_signal <= to_std_logic(slv1 > slv2);
The other way round, std_logic to boolean is most easily done inline as you need it:
my_boolean <= (my_std_logic = '1');
You've already found that conditional functions such as "if" must have a boolean argument. It's often OK to write things such as:
if CARRY = '1' then COUNT <= COUNT + 1;
end if;
But if CARRY is a boolean type
if CARRY then COUNT <= COUNT + 1;
end if;
A reminder that boolean signals can only take 2 values: true or false. As against std_logic whch usually takes the values 0 or 1. Though it can take others such as U (undefined).
www.borinsky.co.uk Jeffrey Borinsky www.becg.tv
