11-03-2017, 09:24 PM
Just a update as to what is happening with this project as progress is slow.
I intend to improve the interpolater from the simple 50:50 one that I am using to a proper two line one. Doing this using schematic entry seemed difficult so I have decided to try and learn some VHDL.
I have learned a tiny bit, enough to rewrite the schematic I have in VHDL.
Just for comparison I have uploaded a file that replaces the schematic that I uploaded earlier in this tread.
In order to have more resources to play with I have ordered a Cyclone IV EP4CE6 FPGA. It has over 6000 cells a opposed to the CPLD which has 192. Even though the FPGA has 270kbit of RAM I will be sticking to the frame stores that I have for now at least.
When I get the interpolater sorted one thing I would like to do is make the aspect ratio switchable between 4:3 and 5:4. It would seem straightforward enough to do. The active video signal from the decoder is programmable and could be used to chop the beginning and end from each line, when in 5:4 mode.
The 405 clock would need to be reduced in frequency when on 5:4 in order to stretch the reduced number of pixels to fill the full line. To do this, I was thinking of using a AD9851 DDS module as the 405 clock source.
Frank
I intend to improve the interpolater from the simple 50:50 one that I am using to a proper two line one. Doing this using schematic entry seemed difficult so I have decided to try and learn some VHDL.
I have learned a tiny bit, enough to rewrite the schematic I have in VHDL.
Just for comparison I have uploaded a file that replaces the schematic that I uploaded earlier in this tread.
In order to have more resources to play with I have ordered a Cyclone IV EP4CE6 FPGA. It has over 6000 cells a opposed to the CPLD which has 192. Even though the FPGA has 270kbit of RAM I will be sticking to the frame stores that I have for now at least.
When I get the interpolater sorted one thing I would like to do is make the aspect ratio switchable between 4:3 and 5:4. It would seem straightforward enough to do. The active video signal from the decoder is programmable and could be used to chop the beginning and end from each line, when in 5:4 mode.
The 405 clock would need to be reduced in frequency when on 5:4 in order to stretch the reduced number of pixels to fill the full line. To do this, I was thinking of using a AD9851 DDS module as the 405 clock source.
Frank
