22-02-2017, 07:32 PM
Hi Jeffery
Thanks for the VHDL file, I have downloaded it and when I get a chance I will study it.
I have uploaded a screen shot of part of the CPLD schematic that I am currently using. This part controls the writing to memory. All the inputs are on the left and all except “FREEZ_FRAME” are from the video decoder. The outputs on the right go to the FIFO's. The Data clock of the video decoder is the FIFO's write clock.
Frank
Thanks for the VHDL file, I have downloaded it and when I get a chance I will study it.
I have uploaded a screen shot of part of the CPLD schematic that I am currently using. This part controls the writing to memory. All the inputs are on the left and all except “FREEZ_FRAME” are from the video decoder. The outputs on the right go to the FIFO's. The Data clock of the video decoder is the FIFO's write clock.
Frank
