Standards converters

[ppppenguin]

Assuming the 405 to 625 project goes ahead the first step is to lash something together that will get the 405 signals digitised and into the FPGA on the main PCB. Then I can do a rough conversion to 625, possibly without interpolations or line creation. This will result in the 377 active lines of a 405 line picture being displayed as part of the 576 in a 625 picture. Doing the line creation and interpolation isn't hard in the FPGA, much of the VHDL from the 625 to 405 converter will be re-used.


The important stuff is optimaising the performance of the 405 front end. I'll be dealing with high quality 405 source material so full bandwidth is essential. It would be nice to oversample the input at 2x or 4x (approx 16MHz or 32MHz) but in practice I'll start without oversampling and see how it looks. I'll probably need a good 3MHz low pass filter to prevent aliasing but I think I have an old Matthey one around. If I oversample at the ADC the analogue filtering will be minmal but I'll need to do a digital LPF in the FPGA. This can use a lot of FPGA resource to do a good job, espeically as the XC2S200 doesn't have any dedicated multipliers.

Guess what will be providing the 405 line test signals for my experiments (Hint, it won't be my own converter because that will be busy doing other things)