07-05-2015, 11:05 AM
More on this - no one has commented yet that as long as pin 2 (trigger) is kept low, the output will be active and the bell will keep ringing.
This MAY NOT BE DESIRABLE
If you want to enforce the length of ring to being only the monostable pulse length, regardless of how long the button is pressed, a few simple extra components will ensure this:
Please excuse the rough diagram - I only have LTspice on this computer - What happens here is that when the button is pressed, a short negative spike is generated on pin 2 (trigger), followed by a +ve spike as the button is released - the +ve spike is clamped by D1 to 0.6V above Vcc and is unimportant. With the values given, you will have a pulse width range from about 2.5s to 7.7s. See the simulation below of what will be seen on pin 2 (trigger) when the button is pressed...
This simple addition will add a whole bunch of noise immunity to the circuit for about 10pence with the additional benefit of not driving you nuts if someone keeps their finger on the button !!
Most data sheets also recommend decoupling the supply to the 555 as close to the chip as is possible with a 100n ceramic plus a 1uF electrolytic. Again, cheap, so do it.
From a "Muntzing" point of view, it's worth noting that 555s can source 200mA and sink 50mA from pin 3, so the output transistor is not necessary at all as we are only sourcing about 50mA - the freewheeling/flyback diode around the relay is still required.
ALSO: A point often missed - The 220uF capacitor discharges rapidly through pin 7 as soon as it reaches 2/3rds of Vcc - internally, there is just an NPN transistor to GND - peak currents of over 1A can be expected - although there seems to be no specification of how much pin 7 can sink, the other pins sink much less, so I have included R5 for safety (a common thing to do) - this limits the discharge current to about 100mA (*) and doesn't impact the timing. Some of the manufacturers' datasheets for their variants of the 555 state that you don't need to current limit pin 7 so long as the total package power budget is not exceeded - I include limiting as a) it's cheap, and b) you don't necessarily know whose implementation of the 555 you are using, so being sure is both cheap and good practice !!
EDIT: Updated schematic and full LTspiceIV card deck attached as "555.txt" - rename to "555.asc" and open with LTspiceIV
Hah!
(*) I = V/R = (0.666*Vcc-0.3)/47 = 120mA. The "-0.3" allows for the Vce[sat] of the 555's internal discharge transistor. In practice, the ESR of the capacitor and other losses reduce the current to about 100 to 110mA.
This MAY NOT BE DESIRABLE
If you want to enforce the length of ring to being only the monostable pulse length, regardless of how long the button is pressed, a few simple extra components will ensure this:
Please excuse the rough diagram - I only have LTspice on this computer - What happens here is that when the button is pressed, a short negative spike is generated on pin 2 (trigger), followed by a +ve spike as the button is released - the +ve spike is clamped by D1 to 0.6V above Vcc and is unimportant. With the values given, you will have a pulse width range from about 2.5s to 7.7s. See the simulation below of what will be seen on pin 2 (trigger) when the button is pressed...
This simple addition will add a whole bunch of noise immunity to the circuit for about 10pence with the additional benefit of not driving you nuts if someone keeps their finger on the button !!
Most data sheets also recommend decoupling the supply to the 555 as close to the chip as is possible with a 100n ceramic plus a 1uF electrolytic. Again, cheap, so do it.
From a "Muntzing" point of view, it's worth noting that 555s can source 200mA and sink 50mA from pin 3, so the output transistor is not necessary at all as we are only sourcing about 50mA - the freewheeling/flyback diode around the relay is still required.
ALSO: A point often missed - The 220uF capacitor discharges rapidly through pin 7 as soon as it reaches 2/3rds of Vcc - internally, there is just an NPN transistor to GND - peak currents of over 1A can be expected - although there seems to be no specification of how much pin 7 can sink, the other pins sink much less, so I have included R5 for safety (a common thing to do) - this limits the discharge current to about 100mA (*) and doesn't impact the timing. Some of the manufacturers' datasheets for their variants of the 555 state that you don't need to current limit pin 7 so long as the total package power budget is not exceeded - I include limiting as a) it's cheap, and b) you don't necessarily know whose implementation of the 555 you are using, so being sure is both cheap and good practice !!
EDIT: Updated schematic and full LTspiceIV card deck attached as "555.txt" - rename to "555.asc" and open with LTspiceIV
(07-05-2015, 09:30 AM)Mark Hennessy Wrote: ...But hopefully it's all good now
Hah!
(*) I = V/R = (0.666*Vcc-0.3)/47 = 120mA. The "-0.3" allows for the Vce[sat] of the 555's internal discharge transistor. In practice, the ESR of the capacitor and other losses reduce the current to about 100 to 110mA.
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