13-06-2013, 10:36 AM
Al is right - in an ideal world, you want the FETs to have binary operation - either ON or OFF.
If they operate in their linear region, they are effectively resistors and will heat up due to the current flowing through them. The minimum resistance they can show is the RDSon figure from the data sheet - that is their drain-source resistance when fully on. To get low RDSon, you generally need a large die size and modern designs which can result in RDSon figures in the low milliohms. The IRF2807 is an very nice FET - pretty good for this application - lowish Qg (total gate charge), low RDSon (which leads to decent current rating for the case size), decent Vdss (perfectly adequate for this application).
I wouldn't expect particularly high efficiency out of this circuit - perhaps 50 or 60% - so assume maybe 40 - 50% of the power you put in is being lost as heat. Stuff will warm up.
Regarding the parasitic oscillation, try using a ferrite bead over the gate leads, close to the FETs - the parasitics are at RF frequencies and the bead will help damp those. Also, constructional techniques make a big difference - do you have a photo of your layout? I would also consider using a low value resistor (between 4.7 & 100 ohms or thereabouts) in the gate leads close to the FET - equivalent to a grid-stopper in valves... I used to design SMPSs and care-and-feeding of FETs is important...
If they operate in their linear region, they are effectively resistors and will heat up due to the current flowing through them. The minimum resistance they can show is the RDSon figure from the data sheet - that is their drain-source resistance when fully on. To get low RDSon, you generally need a large die size and modern designs which can result in RDSon figures in the low milliohms. The IRF2807 is an very nice FET - pretty good for this application - lowish Qg (total gate charge), low RDSon (which leads to decent current rating for the case size), decent Vdss (perfectly adequate for this application).
I wouldn't expect particularly high efficiency out of this circuit - perhaps 50 or 60% - so assume maybe 40 - 50% of the power you put in is being lost as heat. Stuff will warm up.
Regarding the parasitic oscillation, try using a ferrite bead over the gate leads, close to the FETs - the parasitics are at RF frequencies and the bead will help damp those. Also, constructional techniques make a big difference - do you have a photo of your layout? I would also consider using a low value resistor (between 4.7 & 100 ohms or thereabouts) in the gate leads close to the FET - equivalent to a grid-stopper in valves... I used to design SMPSs and care-and-feeding of FETs is important...
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