13-06-2013, 10:25 AM
Thanks Mike. Never mind about CAD: whenever I have sent my D-I-Y ccts. in to any forum, they're always been scanned copies of hand-drawn ccts. What matters is clarity of drawing and the detail therein: your drawing meets those requirements. √
Looking at the waveforms that you sent in, the gate waveform seems to show signs of parasitic oscillation. At the rising edge of that waveform you can see some 'jaggedness' to that waveform: a sure sign of parasitic osc. This will reduce the power efficiency of the FETs, since they will not be acting as pure switches - which is what is required: they will spend some time in a 'linear mode' - thus dissipating heat.
Apparently, MOSFETS are prone to parasitic oscillation. I cannot give you any ready-made solutions to prevent that osc., (my experience with power FETs is very limited), but improved decoupling may help and perhaps low-value resistors (say 4.7 ohms as a starting value) in each drain may also help. Of course, the physical layout will be important: check the 0v. earthing arrangements: ideally, single-point earthing and substantial R.F. earth / 0v. conductors.
As regards half-wave and full-wave rectification, since with half-wave rect. one half of the waveform isn't 'doing anything', then the input impedance of that cct. will be higher than that for a full-wave rect. And that implies that wire of thicker diameter for the coil sourcing that current will help. Of course, at the same time, the power demand from the driving source will be higher, which, in turn, requires that the impedance of that source needs to be lower than that for a half-wave rect. scheme. And that, in turn, could place an even higher demand on that driving source for good R.F. dynamic stability: i.e. freedom from parasitic oscillations.
Which brings me neatly back to where I came in.
HTH,
Al.
Looking at the waveforms that you sent in, the gate waveform seems to show signs of parasitic oscillation. At the rising edge of that waveform you can see some 'jaggedness' to that waveform: a sure sign of parasitic osc. This will reduce the power efficiency of the FETs, since they will not be acting as pure switches - which is what is required: they will spend some time in a 'linear mode' - thus dissipating heat.
Apparently, MOSFETS are prone to parasitic oscillation. I cannot give you any ready-made solutions to prevent that osc., (my experience with power FETs is very limited), but improved decoupling may help and perhaps low-value resistors (say 4.7 ohms as a starting value) in each drain may also help. Of course, the physical layout will be important: check the 0v. earthing arrangements: ideally, single-point earthing and substantial R.F. earth / 0v. conductors.
As regards half-wave and full-wave rectification, since with half-wave rect. one half of the waveform isn't 'doing anything', then the input impedance of that cct. will be higher than that for a full-wave rect. And that implies that wire of thicker diameter for the coil sourcing that current will help. Of course, at the same time, the power demand from the driving source will be higher, which, in turn, requires that the impedance of that source needs to be lower than that for a half-wave rect. scheme. And that, in turn, could place an even higher demand on that driving source for good R.F. dynamic stability: i.e. freedom from parasitic oscillations.
Which brings me neatly back to where I came in.
HTH,
Al.
