16-05-2024, 11:51 AM
HI Mike
In the 2 threads I linked to in post #100 you may find an explanation.
As far as I remember the DC bias disables the sync clamp within the chip and sets the unmodulated carrier level.
Frank
In the 2 threads I linked to in post #100 you may find an explanation.
As far as I remember the DC bias disables the sync clamp within the chip and sets the unmodulated carrier level.
Frank







