405 lines from Raspberry Pi 5

[Mike Watterson]

This might seem like a stupid idea or silly question.
The choices of audio carrier offset are preset, but everything seems to be divided from a 4 MHz master clock, with some PLLs. The audio uses a 31.25 Khz or 62.5 KHz reference for the PLL and divider, and selection of and offset of 4.5, 5.5, 6.0 or 6.5 MHz from the video carrier, rather than setting the frequency direct as with the video modulator. The range is 30 MHz to 450 MHz or 471.25 MHz to 855.25.

So if a reference other than 4 MHz is used, will if still work, but simply every frequency be scaled by the percent change?
So would reducing 4 MHz to 3.111111 MHz give 3.5 MHz offset between carriers when you select 4.5 MHz?
Obviously all the channels would be 3.5/4.5 lower,

System A frequencies vs ch on cols 1 & 2
Ch Video Audio A Audio N Video 2 Audio 2
4.5 0.7777777777777778
1 45 41.5 49.5 35.000 38.500
2 51.75 48.25 56.25 40.250 43.750
3 56.75 53.25 61.25 44.139 47.639
4 61.75 58.25 66.25 48.028 51.528
5 66.75 63.25 71.25 51.917 55.417
6 179.75 176.25 184.25 139.806 143.306
7 184.75 181.25 189.25 143.694 147.194
8 189.75 186.25 194.25 147.583 151.083
9 194.75 191.25 199.25 151.472 154.972
10 199.75 196.25 204.25 155.361 158.861
11 204.75 201.25 209.25 159.250 162.750
12 209.75 206.25 214.25 163.139 166.639
13 214.75 211.25 219.25 167.028 170.528

i,e. 4 MHz replaced by 3.111111, selected 4.5 MHz offset is then 3.5 MHz and last two columns are frequencies you get setting frequency in first column.
The 31.25 / 62.5 KHz would be 24.306 and 48.611 kHz approximately?

"The reference divider is a fixed divide-by-128, resulting in a reference frequency of 31.25 kHz with a 4.0-MHz crystal."
"For low-frequency testing or VHF range operation (test mode 1, states 1.b to 1.e) the UHF oscillator can be internally divided by 2, 4, 8, or 16."

The steps in UHF mode are 250 KHz with 4 MHz reference. The VHF steps with divide by 16 are thus 15.625 KHz
N0–N11: UHF frequency programming bits, in steps of 250 kHz. See Section 15.7, “UHF PLL Section,” for more information.
Table 17 lists bits X2 X1 X0 = 1 0 0 for RF/16 (the 30 MHz to 54 MHz @ 4MHz)
0 1 0 is RF/4, so 117 MHz to 213 MHz

I think the 471.25 MHz to 855.25 becomes 366.334 MHz to 665 MHz with the 3.1111MHz external clock.
30 MHz to 54 MHz -> 23.333 to 42 MHz, which is too low. Using RF/8 gives 46.666 to 84 MHz. The steps will be 24.306 Khz approx instead of 31.25 KHz
The RF/2 ratio will give about 182 MHz to 332.5 MHz with 97 kHz steps

Probably I'm misunderstanding something?