Standards converters

[ppppenguin]

Some of you will have seen my writings on standards conversion. There's a fair bit in the articles on my website. I have also written about my own experiments in other forums. Now I'd like to pick up the threads here.

Using a FPGA (Xilinx XC2S200) based video provessing board that I designed for a client some years ago I put together a simple but fairly high performance 625 to 405 converter. I will try and put some notes about it here, for those who don't have access to my work elsewhere. Here's a photo of the main PCB. The FPGA is under the heatsink near top right, a couple of SDRAM chips below it are for framestores. An 8051 class CPU at bottom centre with a Xilinx CPLD mopping up the interface logic. 54MHz VCXO at middle right.

The plug in modules from left to right are:
Analogue video input
SDI input
Bodged up DAC for 405 output
SDI output for 625 output during experiments.

Looks like I'll soon be doing some 405 to 625 experiments. This is because a company has asked me about recovering some archive 405 line quadruplex tapes. The only real problem is the video input. Modern decoder chips can't handle 405 video so it's a DIY job. Needs ADC, sync separator and clock phaselock. None is especially complex but care needed to get good results. I'm hoping to find an example of a little digitiser PCB I designed c1992 for a client. THis took the analogue output of their VTR leader clock and gave SDI output. It contains all the bits I need though I don't need the SDI interface or PLD. I'll just be taking raw data on a ribbon cable across to the main board. Part of schematic attached.

Won't be doing any more on it for a few weeks but I'll write up the results here.

[ppppenguin]

Assuming the 405 to 625 project goes ahead the first step is to lash something together that will get the 405 signals digitised and into the FPGA on the main PCB. Then I can do a rough conversion to 625, possibly without interpolations or line creation. This will result in the 377 active lines of a 405 line picture being displayed as part of the 576 in a 625 picture. Doing the line creation and interpolation isn't hard in the FPGA, much of the VHDL from the 625 to 405 converter will be re-used.


The important stuff is optimaising the performance of the 405 front end. I'll be dealing with high quality 405 source material so full bandwidth is essential. It would be nice to oversample the input at 2x or 4x (approx 16MHz or 32MHz) but in practice I'll start without oversampling and see how it looks. I'll probably need a good 3MHz low pass filter to prevent aliasing but I think I have an old Matthey one around. If I oversample at the ADC the analogue filtering will be minmal but I'll need to do a digital LPF in the FPGA. This can use a lot of FPGA resource to do a good job, espeically as the XC2S200 doesn't have any dedicated multipliers.

Guess what will be providing the 405 line test signals for my experiments (Hint, it won't be my own converter because that will be busy doing other things)

[Murphyv310]

Hi.
A little off topic but a reminder to the unwary. There are fake auroras occasionally seen on eBay, avoid them like the plague, whether eBay have sorted the problem now I don't know. I've complained and had to close my long standing eBay account due to harassment from the seller. So beware, I cannot elaborate any further for legal reasons.